Data processing apparatus, method of controlling the same, and storage medium storing program

ABSTRACT

A data processing apparatus which circulates a packet on a ring bus by connecting a plurality of communication modules to the ring bus and causing each communication module to send the packet to an adjacent communication module in synchronism with a predetermined periodical signal includes a plurality of data process modules each connected to a corresponding one of the plurality of communication modules to process data held in the packet, and an input/output module connected to at least one of the plurality of communication modules to receive/output data from/to the communication module. The number of circulations of data through the ring bus, which is input from the input/output module to one of the communication modules, until the data completes a predetermined processing and is received by the input/output module is acquired. The frequency of the periodical signal is changed in accordance with the number of circulations.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a data processing apparatus using aring bus, a method of controlling the same, and a storage medium storinga program.

2. Description of the Related Art

Conventionally, there exists a data processing method which executesdata processing using a bus-type pipeline connection formed by arrangingprocessing circuits in parallel. In this connection scheme, data inputfrom an external memory or an external I/F to the input terminal isprocessed in the connection order and output from the output terminal toan external memory or the like. In this case, it is impossible to changethe process order even if the user wants to.

For this purpose, Japanese Patent Laid-Open No. 01-023340 proposes amethod of connecting data processing circuits using a ring bus. JapanesePatent Laid-Open No. 63-247858 proposes a technique of executing imagefilter processing in parallel. This technique sends data with anattached control code to the ring bus and controls data reception basedon the control code so that a plurality of processors can receive thedata that overlap in data transfer between the data processing circuits.Various kinds of methods have thus been proposed to change the order inthe ring bus.

Conventionally, however, if a data process order that does not complywith the connection order is set in ring bus connection, the data flowin the communication path between process modules in the ring bus mayhave an overlapping section, and communication of one of the processmodules may be forced to wait. In the overlapping section, since theamount of transmission data increases, the performance of thecommunication process is poor.

SUMMARY OF THE INVENTION

An aspect of the present invention is to eliminate the above-mentionedproblems with the conventional technology.

The present invention provides a data processing technique of preventingdegradation in process performance even when a data process order notcomplying with the connection order of the process modules is set in aring bus.

The present invention in its first aspect provides a data processingapparatus which circulates a packet on a ring bus by connecting aplurality of communication modules to the ring bus and causing eachcommunication module to send the packet to an adjacent communicationmodule in synchronism with a predetermined periodical signal,comprising: a plurality of data process modules each connected to acorresponding one of the plurality of communication modules to processdata held in the packet; an input/output module connected to at leastone of the plurality of communication modules to receive/output datafrom/to the communication module; an acquisition unit configured toacquire the number of circulations of data through the ring bus untilthe data completes predetermined processing and is received by theinput/output module, the data being input from the input/output moduleto one of the communication modules; and a change unit configured tochange a frequency of the periodical signal in accordance with thenumber of circulations.

The present invention in its second aspect provides a data processingapparatus which circulates a packet on a ring bus by connecting aplurality of communication modules to the ring bus and causing eachcommunication module to send the packet to an adjacent communicationmodule in synchronism with a predetermined periodical signal,comprising: a plurality of data process modules each connected to acorresponding one of the plurality of communication modules to processdata held in the packet; an input/output module connected to at leastone of the plurality of communication modules to receive/output datafrom/to the communication module; a measuring unit configured to measurean amount of data flowing through the ring bus; and a change unitconfigured to change a frequency of the periodical signal based on thedata amount measured by the measuring unit.

The present invention in its third aspect provides a method ofcontrolling a data processing apparatus which circulates a packet on aring bus by connecting a plurality of communication modules to the ringbus and causing each communication module to send the packet to anadjacent communication module in synchronism with a predeterminedperiodical signal, comprising: a plurality of data processing steps ofcausing data process modules each connected to a corresponding one ofthe plurality of communication modules to process data held in thepacket; an input/output step of receiving/outputting data from/to atleast one of the plurality of communication modules; an acquisition stepof acquiring the number of circulations of data input in theinput/output step through the ring bus until the data completespredetermined processing and is output; and a change step of changing afrequency of the periodical signal in accordance with the number ofcirculations.

It is possible to suppress degradation in process performance even whena data process order not complying with the connection order of processmodules is set in a ring bus.

Further features of the present invention will become apparent from thefollowing description of exemplary embodiments with reference to theattached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the arrangement of a module connectedto a ring bus;

FIG. 2A is a view showing the format of packet data;

FIG. 2B is a block diagram showing the arrangement of a ring bus and amodule using it;

FIG. 3 is a block diagram showing the arrangement of a data processingsystem;

FIG. 4 is a view showing data transfer through the ring bus inaccordance with a process order complying with a connection order;

FIGS. 5A and 5B are views showing data transfer through the ring bus inaccordance with a process order not complying with the connection order;

FIGS. 6A and 6B are views showing data transfer through the ring bus inaccordance with the process order not complying with the connectionorder when the operation speed of the ring bus doubles;

FIGS. 7A and 7B are flowcharts illustrating the processing procedure ofring bus operating frequency setting processing;

FIG. 8A is a block diagram showing the arrangement of a ring bus;

FIG. 8B is a view showing the format of packet data;

FIG. 9 is a flowchart illustrating the processing procedure of the datacirculation count measuring unit of the ring bus;

FIG. 10 is a block diagram showing the arrangement of a ring bus andmodules connected to it; and

FIG. 11 is a flowchart illustrating the processing procedure of the dataamount measuring unit of the ring bus.

DESCRIPTION OF THE EMBODIMENTS

Preferred embodiments of the present invention will now be describedhereinafter in detail, with reference to the accompanying drawings. Itis to be understood that the following embodiments are not intended tolimit the claims of the present invention, and that not all of thecombinations of the aspects that are described according to thefollowing embodiments are necessarily required with respect to the meansto solve the problems according to the present invention. The samereference numerals denote the same continent elements, and a descriptionthereof will not be repeated.

First Embodiment

FIG. 1 shows the arrangement of a module according to the firstembodiment.

A single module 100 is connected to a ring bus. A ring bus 110circulates data in a single direction. A communication unit 120transmits/receives data between the ring bus and the module, and alsoholds a data packet flowing on the ring bus. A data processing unit 130processes data received by the communication unit 120.

In the communication unit 120, a receiving unit 121 receives data to beprocessed by the module from data packets flowing on the ring bus. Fordata processed by the data processing unit 130 or data which willundergo some processing by the communication unit 120, a transmittingunit 122 generates a transfer packet and outputs it. A selector 123selects and outputs, based on determination of the transmitting unit122, one of a packet input from the ring bus 110 and a packet generatedby the transmitting unit 122.

A buffer 124 temporarily holds the output from the selector 123.Temporarily holding data to be connected to the ring bus is done by thebuffer 124. A communication unit clock supply unit 125 supplies a clocknecessary for the operation of the communication unit 120. Thecommunication unit clock supply unit 125 supplies, to the communicationunit 120, a clock having a frequency designated by an operatingfrequency designation unit 126, which designates the operating frequencyin accordance with an external setting.

Note that the clock frequency is often a multiple of an integer multipleof a specific original oscillation frequency or an integer fraction ofthe oscillation frequency, which is a commonly used technique.Additionally, in general, to avoid a problem associated withcommunication path synchronization, the original oscillation frequencyis raised in advance, and control is performed to switch the frequencyto a low one corresponding to an integer fraction or a factor of a powerof 2. However, restrictions in implementing the generated frequenciesare not directly relevant to the intention and effects of the presentinvention. Hence, in the description of the present invention, there areno restrictions imposed concerning the oscillation frequency andfrequencies that can be designated in particular.

If a frequency calculated in the description of the embodiment does notexist as an actually selectable frequency, a frequency higher than andclosest to the calculated frequency is selected and designated. This isto suppress a data delay on the communication path by raising theoperating frequency of the communication path and thus increasing theapparent data amount that can be held on the communication path.

In addition to the communication unit clock supply unit 125 illustratedin FIG. 1, means for appropriately supplying clocks to the dataprocessing unit and other components exist. However, these means are notillustrated because they provide no remarkable effect in the presentinvention. These clock supply means supply an operation clock(periodical signal for driving; to be simply referred to as a clockhereinafter) having a specific period (frequency). How each clock supplymeans corresponding to a processing means decides the operatingfrequency will not be mentioned in this embodiment. However, each clocksupply means corresponding to a processing means supplies a clockindependently of the communication unit clock supply means.

FIG. 2A shows the structure of a packet circulating through the ringbus. Reference numeral 200 denotes an entire packet. A valid flag 201represents whether the packet is valid. A stall flag 202 represents thatthe packet cannot be received and is therefore put on hold. A node ID203 indicates the transmission source of the data. A count value 204represents the data transmission order. Reference numeral 205 denotestransmission data.

The operation of the ring bus in the example of the image process module100 will be described below. When outputting data to the ring bus,first, the valid flag 201 of each input packet held in the buffer 124 ofthe ring bus is detected to search for an invalid packet (empty packet).If the valid flag 201 of an input packet indicates “valid”, the inputpacket is stored in the buffer 124 and output to the ring bus at thenext clock.

On the other hand, if the valid flag 201 of an input packet indicates“invalid”, and there is outputtable data processed by the dataprocessing unit of the module, the following packet is generated, heldin the buffer 124, and output to the ring bus. More specifically, thispacket is generated by adding, to the outputtable data, the valid flag201 (“valid”), the stall flag 202 (“invalid”), the module ID of its own(node ID), and the count value of the number of output data. When thepacket is output to the ring bus, the output counter is incremented.

On the data receiving side, the valid flag 201, node ID 203, and countvalue 204 of the input packet are monitored. Assume that a packet havingthe valid flag 201 indicating “valid”, the node ID 203 matching a presetstandby ID, and the count value 204 matching the input counter value isinput. If the data processing unit 130 can receive data, the inputpacket is received by the data processing unit 130. After changing thevalid flag 201 to “invalid”, the packet is output to the next buffer. Atthis time, the counter for counting the number of input data isincremented, and the input counter value is updated.

If the data processing unit 130 in the module cannot receive data, thepacket is output to the buffer 124 after changing only the stall flag202 of the input packet to “valid” (that is, data reception is put onhold) without changing the remaining fields. Note that the input counterand the output counter are initialized to the same value before thestart of data transfer to ensure synchronization.

FIG. 2B shows an arrangement example in which the ring bus is formed byconnecting individual modules described with reference to FIG. 1.Reference numeral 300 denotes a ring bus. A terminal module 310packetizes external data received through a connection 360 to anexternal data bus, and submits the packet to the ring bus 300. Theterminal module 310 also has a function of extracting data that hasundergone packet processing in a module connected to the ring bus, andexternally outputting the packet via a connection 350 to the externaldata bus.

Modules 320, 330, and 340 are connected to the ring bus. The adjacentmodules 310, 320, 330, and 340 respectively include communication units311, 321, 331, and 341 each serving as a communication module thattransmits/receives data to/from the ring bus, and data processing units312, 322, 332, and 342 which perform processing for individual modules.The data processing units can perform either different processes for therespective modules or the same process for several modules.

A ring bus formed by four modules will be exemplified here. However, thenumber of modules that construct the ring bus is not particularlyrestricted; the ring bus may be formed using four or more modules. Thecommunication unit clock supply unit 125 supplies a clock to thecommunication units 311, 321, 331, and 341 in accordance with anoperating frequency preset by the operating frequency designation unit126. The clock supply allows the communication units 311, 321, 331, and341 and the data bus that connects the communication units to performdata communication in synchronism with the supplied clock.

FIG. 3 shows an example of the arrangement of a system in which a dataprocessing apparatus is arranged. A system control unit 400 includes aCPU 401 for calculation and control, a ROM 402 storing permanent dataand programs, a RAM 403 to be used to temporarily store data or loadprograms, and an external storage device 404 which holds external data.

A data input unit 410 receives data to be processed from outside of thesystem or from the system control unit. The data input unit 410 may bean image reading apparatus formed from devices such as an image scannerand an A/D converter or a voice input apparatus formed from devices suchas a microphone and an A/D converter. The data input unit 410 may be aDMA (Direct Memory Access) module which reads out data from the systemcontrol unit or a memory arranged outside, as a matter of course.

Reference numeral 420 denotes a data processing apparatus. A data outputunit 430 outputs data processed by the system to the outside or thesystem control unit. For example, the data processing apparatus 420 maybe an image output apparatus including a printer device that convertsimage data into a dot pattern and outputs it, or a voice outputapparatus which outputs voice data via a D/A converter and the like. Thedata output unit 430 may be a DMA module which writes data in the systemcontrol unit or a memory arranged outside.

Data input to the data input unit 410 may be sent to the system controlunit and processed by the CPU 401, or directly temporarily stored in theRAM 403 or the external storage device 404. Hence, the data processingapparatus 420 may directly receive input data from the data input unit410 and process it, or perform processing in accordance with aninstruction and data supply from the system control unit 400.

The output from the data processing apparatus 420 may be sent to thesystem control unit 400 again, or directly sent to the data output unit430. The data processing apparatus 420 operates based on various kindsof data processing contents set and various process data supplied underthe control of the system control unit 400.

An example of an operating frequency calculation method will bedescribed next with reference to FIG. 4. Referring to FIG. 4, “a”represents a state wherein eight modules are connected to a ring bus. Inthe ring bus with this connection, data submitted from a datainput/output module 501 (to be referred to as a “module TE0”hereinafter) to the ring bus is first processed by a data process module502 (to be referred to as a “module PE1” hereinafter). After theprocessing, a data process module 503 (to be referred to as a “modulePE2” hereinafter) processes and outputs the data. The process module useorder is thus set in advance. Note that as shown in FIG. 4, the timenecessary for data to move from “a” to “b” is defined as T. The dataprocess time of each data module shown in FIG. 4 is uniformly assumed tobe 2T.

That is, in this case, the process order complies with the connectionorder. The module TE0 corresponds to the module 310 in FIG. 2B. Themodules 502 and 503 correspond to the modules 320, 330, and 340 in FIG.2B. These process modules are simply illustrated for the description ofthe data operation in the ring bus.

In FIG. 4 that is an explanatory view of the embodiment, data istransferred through the ring bus counterclockwise in one direction. Data504 is submitted first in “b” of FIG. 4 and then circulated through thering bus counterclockwise, as indicated by “c” and “d” of FIG. 4. In “d”of FIG. 4, the module PE1 502 receives data 505 for processing.

In the description of this embodiment, the modules PE1 and PE2 endprocessing in 2T. Hence, in “f” of FIG. 4 after the elapse of 2T from“d” of FIG. 4, the module PE1 sends processed data 506 to the ring busand instead receives next process data 507. After that, the processeddata 506 sent from the module PE1 sequentially moves through the ringbus from “f” to “h” of FIG. 4. In “h” of FIG. 4, the module PE2 in itsturn to process according to the process order receives process data508. The data is similarly input from the module TE0, though the twomovements between “g” and “h” of FIG. 4 are not illustrated.

The module PE2 also ends processing in 2T. After that, in “j” of FIG. 4,the module PE2 sends processed data 509 to the ring bus and insteadreceives next process data 510. The sent processed data 509 then movesthrough the ring bus from “j” to “l” of FIG. 4. When arriving at themodule TE0, the processed data is output to the outside as output data511.

As described above, when the process order is set based on theconnection order, data is processed and output in one circulation. Asindicated by “m” to “u” of FIG. 4, data are then output at the interval2T. In addition, the ring bus always has four empty packets thattransfer no data, like a packet 512. As can be seen from this, the ringbus can steadily transfer data while reserving the capacity.

In this case, one data flow steadily occupies four of the eight packets.Hence, when another data flow different from the above PE combination isformed in the ring bus, the ring bus uses its capacity 100%. That is,the ring bus can transfer two different data flows.

Another example of the operating frequency calculation method accordingto the present invention will be described next with reference to FIGS.5A and 5B. Referring to FIG. 5A, “5 a” represents a state wherein eightmodules are connected to a ring bus. Assume that the ring bus with thisconnection performs processing in a process order different from that inFIG. 4. More specifically, data submitted from a data input/outputmodule 601 (to be referred to as a “module TE0 (FIGS. 5A and 5B)”hereinafter) to the ring bus is first processed by a module 603 (to bereferred to as a “module PE2 (FIGS. 5A and 5B)” hereinafter). Afterthat, a module 602 (to be referred to as a “module PE1 (FIGS. 5A and5B)” hereinafter) processes and outputs the data. The process order isthus designated in advance.

Data 604 is submitted first in “5 b” of FIG. 5A and then circulatedthrough the ring bus counterclockwise, as indicated by “5 c” to “5 h” ofFIG. 5A. In “5 h” of FIG. 5A, the module PE2 (FIG. 5A) receives data 605for processing. The module ends processing in 2T, as described above.Hence, in “5 j” of FIG. 5A after the elapse of 2T from “5 h” of FIG. 5A,the module PE2 sends processed data 606 to the ring bus and insteadreceives next process data 607.

After that, the processed data 606 sent from the module PE2 movesthrough the ring bus from “5 k” to “5 n” of FIG. 5A. In “5 n” of FIG.5A, the module PE1 (FIG. 5A) in its turn to process according to theprocess order receives process data 608. The module PE1 (FIG. 5A) alsoends processing in 2T. After that, in “5 p” of FIG. 5A, the module PE1(FIG. 5A) sends processed data 609 to the ring bus and instead receivesnext process data 610.

The sent processed data 609 then moves through the ring bus from “5 q”to “5 v” of FIGS. 5A and 5B. When arriving at the module TE0 (FIGS. 5Aand 5B), the processed data 609 is output to the outside as output data611. When processing data through such a path, the data transfer clockof the ring bus is given by the speed of transferring data to theimmediately adjacent process module in the time T. At this time, in thesteady state, only one empty transfer packet exists, as indicated by 612in “5 ah” of FIG. 5B. As is apparent from this, little data transfercapacity is left to the ring bus.

As described with reference to FIG. 4, when the process order complyingwith the connection order is designated, and each process moduleexecutes processing in 2T, data on the ring bus exists in every otherpacket. However, in the example shown in FIGS. 5A and 5B in which thereverse order is designated by changing the process order, datacirculates twice through the ring bus and exits using almost all of thedata holding capability of the ring bus. In this state, it is almostimpossible to process another data flow. That is, since the bandoccupancy of the ring bus increases upon changing the process order, theprocess capability of the data processing apparatus halves. That is, theapparatus can process only a single data flow.

The present invention takes measures such that even when the reverseorder is designated by changing the process order, two data flows can beprocessed like when using the normal process order. As a measure, thefirst embodiment discloses a technique of changing the clock frequencythat decides the operation speed of the ring bus. More specifically, thedata transfer clock frequency is raised as the number of datacirculations through the ring bus up to the end of processing increases.That is, the transfer period is changed to be shorter.

FIGS. 6A and 6B show an example in which the data transfer rate of thering bus doubles. The doubled transfer rate is set based on an analysisresult representing that when the process order is set to be opposite indirection to the data flow from the process module PE1 to the modulePE2, input data circulates twice through the ring bus. When the transferrate doubles, the time axis in FIGS. 7A and 7B is expressed by thedouble speed. For example, the elapse time from “6 a” to “6 b” is T inFIGS. 4 to 5B. In FIG. 6A, however, the time necessary for transfer isT/2, that is, ½ the transfer time T in FIG. 4 because the transfer rateof the ring bus doubles. However, since the clock frequency to besupplied to the process modules is not controlled, the ring bus operatesat a speed four times higher than in the conventional process modules.

Referring to FIG. 6A, “6 a” represents a state wherein eight modules areconnected to a ring bus, as in FIGS. 4, 5A and 5B. In the ring bus withthis connection, data submitted from a data input/output module 701 (tobe referred to as a “module TE0 (FIG. 6A)” hereinafter) to the ring busis first processed by a module 703 (to be referred to as a “module PE2(FIG. 6A)” hereinafter). After that, a module 702 (to be referred to asa “module PE1 (FIG. 6A)” hereinafter) processes and outputs the data.The process order is thus designated in advance.

Data 704 is submitted first in “6 b” of FIG. 6A and then circulatedthrough the ring bus counterclockwise, as indicated by “6 c” to “6 h” ofFIG. 6A. In “6 h” of FIG. 6A, the process module PE2 (FIG. 6A) receivesdata 705 for processing. The process module ends processing in 2T, asdescribed above. In this case, however, since the time necessary fordata transfer is T/2, the state indicated by “6 l” of FIG. 6A isobtained after the elapse of 2T from “6 h” of FIG. 6A. At this point oftime, the process module PE2 sends processed data 706 to the ring busand instead receives next process data 707.

After that, the processed data 706 sent from the process module PE2(FIG. 6A) moves through the ring bus from “6 m” to “6 p” of FIG. 6A. In“6 p” of FIG. 6A, the module PE1 (FIG. 6A) in its turn to processaccording to the process order receives process data 708. The processdata 708 has the same contents as those of the processed data 706.

The process module PE1 (FIG. 6A) 702 also ends processing in 2T. Afterthat, in “6 t” of FIG. 6A, the process module PE1 (FIG. 6A) sendsprocessed data 709 to the ring bus and instead receives next processdata 710. The sent processed data 709 then moves through the ring busfrom “6 u” to “6 z” of FIGS. 6A and 6B. When arriving at theinput/output module TE0 (FIGS. 6A and 6B), the processed data is outputto the outside as output data 711.

Note that the input/output module TE0 (FIGS. 6A and 6B) submits data atthe interval 2T, as in FIGS. 4, 5A and 5B. This creates a situation inwhich data is supplied in synchronism with the processing of the modulesPE1 and PE2 (FIGS. 6A and 6B). In “6 n” of FIG. 6A, however, processeddata 712 passes just at the timing the module TE0 (FIGS. 6A and 6B)outputs data. Since it is impossible to put two data in one packet, datasubmission from the module TE0 (FIGS. 6A and 6B) delays by T/2. Thisdelay leads to delay of output in “6 am” of FIG. 6B by T/2 from thenormal interval 2T. However, since four empty packets 713 shown in, forexample, “6 aa” of FIG. 6B exist almost always, the occupancy of data onthe ring bus can be regarded as the same as in the example of FIG. 4.

As described above, when a process order that is the reverse of theconnection order is designated, and data circulates twice through thering bus, the clock that decides the operation speed of the ring bus isdoubled to improve the data transfer capacity of the ring bus and thusobtain a capability of processing another data flow.

An example has been described above in which the process order reverseto the connection order is set in advance to circulate data twicethrough the ring bus. However, even when more data process modules joinin with the processing, and the reverse process order to the connectionorder is set to circulate data N times through the ring bus, the datatransfer capacity of the ring bus can be improved, as in FIGS. 6A and6B. That is, when data circulates N times through the ring bus, theoperation speed of the ring bus is increased to N times, therebyobtaining the same effect as described with reference to FIGS. 4 to 6B.One of the reasons why the operation speed of the ring bus is decidedbased on the number of data circulations through the ring bus is to saveenergy. More specifically, if the speed need not be higher, theoperation speed of the ring bus is kept low, thereby saving powerconsumption of the entire system. For example, when the number ofcirculations is small, the frequency is changed to be lower (the periodis changed to be longer). The number of circulations is a naturalnumber.

In actual circuit implementation, if the clock is raised to be N timeshigher than the fundamental original oscillation frequency (periodicalsignal serving as a reference), the waveform of the clock may beblunted. To prevent this, for example, the fundamental clock is designedin advance to be N times higher than the normal clock by setting theupper limit of the number of circulations. If the number of circulationsis small, the clock may be divided and supplied to control the operationto a low speed. This embodiment has disclosed changing the process speedof the ring bus in accordance with the number of circulations. However,whether the original oscillation frequency is set to N times or 1/Ndepends on the embodiment.

FIGS. 7A and 7B illustrates the processing procedure of causing thecontrol device such as the CPU in FIG. 3 to instruct the operatingfrequency designation unit 126 in FIG. 1 which is provided in the dataprocessing apparatus when the process order reverse to the connectionorder is set. In step S801, processing starts. In step S802, the CPUreads out connection order information O[n] of the process modules. Forexample, O[j] holds the ID of the jth connected module based on theconnection order.

In step S803, the CPU reads out a process order P[n] designated inadvance. For example, P[i] holds the ID of the module which isdesignated as the ith module to perform processing in the process order.In step S804, the CPU initializes a process order search counter i to 0.In step S805, the CPU initializes a variable pos that holds the ordinalnumber of the current process module based on the connection order to 0.Note that an ordinal number representing the connection order or processorder is an integer of 0 or more. Normally, when the module connectedfirst is represented by 0, {0,1,2,3,4, . . . } is defined as a sequencerepresenting the connection order.

In step S806, the CPU initializes the number N of circulations to 0. Instep S807, the CPU initializes a connection order search counter j to 0.In step S808, the CPU determines whether the process module representedby P[i] matches the process module represented by O[j]. If the processmodules match, the process advances to step S810. If the process modulesdo not match, the process advances to step S809. In step S809, the CPUincrements j by one, and the process returns to step S808. In step S810,the CPU compares the variable pos that holds the order of the currentprocess module with j. If pos j, the process advances to step S811.Otherwise, the process advances to step S812.

In step S811, the CPU increments the number N of circulations by one. Instep S812, the CPU substitutes j into pos. In step S813, the CPUincrements i by one. In step S814, the CPU checks whether the search bythe process order search counter i has been done for all modulescomplying with the process order designated in advance. If the searchhas ended, the process advances to step S815. Otherwise, the processreturns to step S807.

In step S815, the CPU sets the frequency of the operating frequencydesignation unit 126 based on the obtained number N of circulations. Forexample, if the operating frequency designation unit 126 is implementedto set a frequency N times higher than the original oscillationfrequency, N is set. If the operating frequency designation unit 126 isimplemented to set a low frequency by dividing the original oscillationfrequency, a frequency N/M is set, where M is the maximum number ofcirculations defined in the specifications. If the operating frequencydesignation unit is implemented to designate a frequency that takesdiscrete values, a designatable frequency not less than and closest toN/M is designated. After that, the process advances to step S816 to endthe setting processing.

In this embodiment, as described above, using the obtained number N ofcirculations, the operating frequency that decides the data transferrate of the ring bus is multiplied by N or divided into N/M using themaximum number M of circulations as well as N. The value of the numberof circulations changes depending on how to implement the operatingfrequency designation unit 126 in FIG. 1 or setting of the originaloscillation frequency, as described above. That is, the value of thenumber of circulations depends on implementation of the operatingfrequency designation unit 126.

In the first embodiment, an example has been described in which theoperating frequency that decides the data transfer rate is controlled.However, the same effect can obviously be obtained by controlling theprocess speed on the side of each data process module. Morespecifically, when the number of data circulations is 2, the transferrate of the ring bus doubles. Instead, the process speed on the side ofeach data process module may be halved without changing the transferrate of the ring bus. Reducing the speed of the data process modules isdone on limited occasions but yields the same effect as described abovein terms of preventing any delay of data processing in the entire ringbus. Note that although in this embodiment the number of circulations isinitialized to 0 for the convenience of processing, the number ofcirculations is basically handled as a natural number.

Second Embodiment

FIG. 8A shows the arrangement of process modules connected to a ring busaccording to the second embodiment. The arrangement in FIG. 8A includestwo new functional units in addition to the arrangement shown in FIG.2B. One is a data circulation count measuring unit 901 which isconnected to the ring bus and monitors valid data on the ring bus so asto count the number of circulations through the ring bus in a routewhere data undergoes processes designated in advance in a single dataflow. The other is an operating frequency designation value calculationunit 902 which obtains a set value for an operating frequencydesignation unit 126 based on the number N of circulations detected andacquired by the data circulation count measuring unit 901.

The arrangement may also include a control signal connection 903 whichsends, to the data circulation count measuring unit 901, a reset signalthat triggers initialization and data flow identification information tobe used for initialization in accordance with the timing of the start orend of a data flow. A reset signal that initializes the entire dataprocessing apparatus or the like may exist throughout the dataprocessing apparatus in accordance with normal implementation. In suchreset control, implementation may be done to reset all numbers of datacirculations upon resetting the entire data processing apparatus. Thedata circulation count measuring unit 901 may receive the initializationinstruction directly from a system control unit 400 or a CPU 401 shownin FIG. 3. In this case as well, the system control unit 400 or the CPU401 may control to selectively initialize only the number ofcirculations of a data flow that is starting or initialize all numbersof circulations. Alternatively, one of the two initialization methodsmay selectively be designated.

FIG. 8B shows an example of a data packet that holds informationnecessary for the data circulation count measuring unit 901 to detectthe number of circulations of data belonging to a single data flow. Thedata packet holds data flow identification information F 1001 serving asinformation for identifying a data flow of different data processing inaddition to the information described with reference to FIG. 2A.

Processing of causing the data circulation count measuring unit 901 todetect and decide the number of circulations using the data flowidentification information F 1001 and a node ID 203 serving as theidentification tag of the node of each module will be explained withreference to FIG. 9. In step S1101, processing starts. In step S1102,the data circulation count measuring unit initializes the number N[f] ofcirculations for a data path f to 0. In step S1103, the unit initializesall valid data process module counts COUNT[f][N] of all data processmodules N to 0.

In step S1104, the unit waits for a data processing start trigger. Whendata processing starts, the process advances to step S1105. In stepS1105, the unit checks input data. In step S1106, the unit determineswhether the data is valid. If the data is valid, the process advances tostep S1107. Otherwise, the process returns to step S1105.

In step S1107, the data circulation count measuring unit refers toCOUNT[F][node ID] based on the node ID 203 and the data flowidentification information F 1001 serving as the identification tag ofthe data flow. If the value is 0, the process advances to step S1108.Otherwise, the process advances to step S1109.

In step S1108, the unit increments the number N[F] of circulations byone. In step S1109, the unit substitutes 1 into COUNT[F][node ID], andthe process returns to step S1105.

In this processing, the state of the ring bus is always monitored duringthe operation of the data processing apparatus. Hence, theabove-described processing is repeated until the data processingapparatus is stopped or initialized again. Initialization may be done atthe timing, for example, the data input/output unit starts or endsspecific data processing. That is, the initialization need not always beperformed at the timing the entire system or entire data processingapparatus is reset to activated.

The data circulation count measuring unit 901 in FIG. 8A monitors aplurality of data flows, as a matter of course. For this reason, whenthe initialization, that is, initialization of the number N ofcirculations in step S1102 is performed at the start or end of aspecific data flow in a data input/output unit 310, the initializationmay be enabled for each flow.

In the processing procedure shown in FIG. 9, the number of circulationsunique to each data flow is detected by incrementing the number ofcirculations by one for specific data with the data flow identificationnumber F 1001 from a specific data process module. In the dataprocessing, the amount of data output from a single data process moduleincreases in accordance with the amount of processed data, as a matterof course. Hence, when continuous processed data from a module which hasbeen counted once is counted, the count value indicates the processeddata amount, as shown in the flowchart of FIG. 11 of the thirdembodiment to be described later.

To prevent this, for example, the number of circulations is countedbased on the node ID 203 of data that passes through the data path ofthe ring bus and returns to the upstream again by the processing asdisclosed in FIG. 9. This allows measurement of how data steadilycirculates through the ring bus.

In the processing example shown in FIG. 9, the number of circulations isobtained separately for the data flow identification information F 1001.It is also effective to convert the sum of the numbers corresponding toall pieces of information F into the number of data circulations in theentire ring bus and use this value for control. This technique can beimplemented by eliminating [f] and [F] in FIG. 9. In this case, however,the node ID 203 is assigned a value that causes no conflict among alldata process modules connected to the ring bus. It is necessary to thuscontrol to prevent any error in counting the number of circulationscaused by repeating the node ID 203 of another data process module incounting.

As described above, the present invention discloses the processing shownin FIG. 9 as an example of the means for detecting the number ofcirculations. There may also be added processing of counting the numberof circulations when a specific process module incapable of receivingdata sets the stall bit and circulates the data put on hold. Thisprocessing can easily be implemented by, for example, monitoring thestall bit shown in FIG. 2A, and upon detecting setting of the bit,incrementing the number N[F] of circulations by a predetermined value orratio. Alternatively, upon detecting setting of the stall bit, the flowID, node ID, and counter value of the packet are held. When a packethaving the same flow ID, node ID, and counter value has returned withits stall bit set, the number N[F] of circulations is furtherincremented, thereby easily accurately detecting the number ofcirculations.

Third Embodiment

FIG. 10 illustrates the arrangement of process modules connected to aring bus according to the third embodiment.

The arrangement in FIG. 10 includes two new functional units in additionto the arrangement shown in FIG. 2B. One is a data amount measuring unit1201 which is connected to the ring bus and monitors valid data on thering bus so as to measure the amount of valid data per predeterminedtime through the ring bus. The other is an operating frequencydesignation value calculation unit 1202 which obtains a set value thatdecides the transfer rate of the ring bus based on a data amount Mdetected by the data amount measuring unit 1201. The set value is sentto an operating frequency designation unit 126.

As in the other embodiments, the reset signal that initializes theentire data processing apparatus or the like may exist throughout thedata processing apparatus in accordance with normal implementation. Insuch reset control, implementation may be done to reset even the helddata amount upon resetting the entire data processing apparatus. Thedata amount measuring unit 1201 may receive the initializationinstruction directly from a system control unit 400 or a CPU 401 shownin FIG. 3.

FIG. 11 illustrates the processing procedure of measuring the dataamount according to the embodiment. In step S1301, processing starts. Instep S1302, the data amount measuring unit reads out a time L in whichdata makes round the ring bus. In step S1303, the unit initializes avariable M representing the data amount on the ring bus.

In step S1304, the unit waits for a data processing start trigger. Uponreceiving the data processing start trigger, the process advances tostep S1305. In step S1305, the unit checks input data. In step S1306,the unit determines whether a predetermined time has elapsed for theinput data until checking the input data is valid. If the time haselapsed, the process advances to step S1309. Otherwise, the processadvances to step S1307 to check whether the input data is valid. Whetheror not the data is valid can be determined by checking a valid flag 201shown in FIG. 2A. Upon determining that the data is not valid, theprocess returns to step S1305. If the data is valid, the processadvances to step S1308.

In step S1308, the unit increments the valid data amount M by one. Theprocess then returns to step S1305. On the other hand, if thepredetermined time has elapsed in step S1306, the unit holds themeasured value M as an output value in step S1309. In step S1310, theunit initializes the data amount M on the ring bus, and the processreturns to step S1305.

This processing also continues until the data processing apparatus isstopped halfway or reset. In step S1309, in addition to the processingof holding, as the output, the valid data amount M measured perpredetermined time, statistical processing of suppressing variations inmeasured values by, for example, averaging the held values of severalpast valid data amounts M may be executed. Alternatively, the measuredvalue of one or two cycles later may be predicted from the past measuredvalues using a specific prediction coefficient or the like, and held asthe output.

The thus held output is read out by the operating frequency designationvalue calculation unit 1202 and compared with a standard data amountgiven to the ring bus per predetermined time. The operating frequency isset by increasing the operating frequency to an integer multiple ordecreasing it to a fraction of an integer in accordance with themagnitude of the data amount measured value M. For example, when thevalid data amount measured value M falls within the range from the valuein the normal state (exclusive) to the double of the value in the normalstate (inclusive), the operating frequency is doubled. Generallyspeaking, when the measured data amount exceeds the standard data amountor (N−1) (N is an integer of 2 or more) times of it and is equal to orsmaller than the N times of the standard data amount, the operatingfrequency designation value calculation unit 1202 sets the operatingfrequency so as to multiply the data transfer rate between the processmodules that perform processing through the ring bus by the integer N.Reversely, when the measured data amount falls below the standard dataamount or 1/N (N is an integer of 1 or more) times of the standard dataamount and is equal to or larger than 1/(N+1) times, the operatingfrequency designation value calculation unit 1202 sets the operatingfrequency so as to divide the data transfer rate between the processmodules that perform processing through the ring bus by the integer N.This allows to improvement of the data processing efficiency. Note thatthe frequency conversion to N or 1/N times is merely an example.Conversion to, for example, 2^(N) or ½^(N) times may be easier from theviewpoint of the hardware configuration. As described above, the presentinvention intends to increase the frequency when the data amountincreases, or decrease the frequency when the data amount decreases. Anysimply increasing or decreasing function is usable as the operationalexpression.

In the actual operation, the waveform may be distorted by frequentoperating frequency switching, leading to errors in data processing. Toprevent this, the operating frequency designation value calculation unit1202 may immediately execute raising the operating frequency but controlthe operating frequency lowering instruction using predeterminedhysteresis processing or the like so as to suppress frequent operatingfrequency switching.

Fourth Embodiment

In this embodiment, an example will be described in which whendesignating the operating frequency for an operating frequencydesignation unit 126, a system control unit 400 obtains and designatesthe set value based on the number F of data flows a data processingapparatus 420 is instructed to simultaneously execute.

As shown in FIGS. 6A and 6B of the first embodiment, when the datatransfer rate of the ring bus doubles, half of the packets become empty,and the data holding capability of the ring bus can be reserved. As isapparent from this, raising the operating frequency enables to increasethe amount of data flowing through the ring bus.

On the other hand, when a plurality of data flows are set in the ringbus, the amount of data flowing through the ring bus increases, as amatter of course. The system control unit can grasp the number F of dataflows to be simultaneously executed by the data processing unit. Hence,the system control unit may control to, for example, set the operatingfrequency of the ring bus to F times of the preceding frequency based onthe grasped number F of data flows.

Actually, when the process order is the reverse of the connection order,the amount of data flowing through the ring bus changes, as describedwith reference to FIG. 4 or 5. For this reason, how to set the frequencycannot be determined based on only the number F of data flows. However,when using the ring bus for the operation, specifying the number ofcirculations through the ring bus in processing not complying with theconnection order allows to control in proportion to the number F offlows.

For example, as shown in FIGS. 6A and 6B of the first embodiment, whenthe process order reverses only once, and two data flows that circulatetwice through the ring bus are to be processed simultaneously, thefrequency that decides the transfer rate may be set to, for example, 2×Ftimes based on the number F of data flows and the number of datacirculations “2”. This makes it possible to implement transfer ratechange considering both the number N of data circulations and the numberF of data flows.

In the example shown in FIGS. 6A and 6B, since both the data processmodules 702 and 703 require the process time 2T, the operating frequencymay be set to F times by dividing 2F described in the fourth embodimentby 2. In the fourth embodiment, the appropriate set value of theoperating frequency may be decided by combining the parameters includingthe number N of data circulations, the number F of data flows to beprocessed simultaneously, and the process time 2T of the data processmodules, thereby obtaining the set value for the operating frequencydesignation means.

Other Embodiments

Aspects of the present invention can also be realized by a computer of asystem or apparatus (or devices such as a CPU or MPU) that reads out andexecutes a program recorded on a memory device to perform the functionsof the above-described embodiment(s), and by a method, the steps ofwhich are performed by a computer of a system or apparatus by, forexample, reading out and executing a program recorded on a memory deviceto perform the functions of the above-described embodiment(s). For thispurpose, the program is provided to the computer for example via anetwork or from a recording medium of various types serving as thememory device (for example, computer-readable medium).

While the present invention has been described with reference toexemplary embodiments, it is to be understood that the invention is notlimited to the disclosed exemplary embodiments. The scope of thefollowing claims is to be accorded the broadest interpretation so as toencompass all such modifications and equivalent structures andfunctions.

This application claims the benefit of Japanese Patent Application No.2010-032902, filed Feb. 17, 2010, which is hereby incorporated byreference herein in its entirety.

What is claimed is:
 1. A data processing apparatus which circulates apacket on a ring bus by connecting a plurality of communication modulesto the ring bus and causing each communication module to send the packetto an adjacent communication module in synchronism with a predeterminedperiodical signal, comprising: a plurality of data process modules eachconnected to a corresponding one of the plurality of communicationmodules to process data held in the packet; an input/output moduleconnected to at least one of the plurality of communication modules toreceive/output data from/to the communication module; an acquisitionunit configured to acquire the number of circulations of data throughthe ring bus until the data completes predetermined processing and isreceived by said input/output module, the data being input from saidinput/output module to one of the communication modules; and a changeunit configured to change a frequency of the periodical signal inaccordance with the number of circulations.
 2. The apparatus accordingto claim 1, wherein said change unit changes the frequency to a higherfrequency as the number of circulations increases.
 3. The apparatusaccording to claim 1, wherein said change unit changes the frequency toa lower frequency as the number of circulations decreases.
 4. Theapparatus according to claim 1, further comprising a clock supply unitconfigured to supply the periodical signal serving as a reference to theplurality of communication modules, Wherein the change unit changes thefrequency of the periodical signal based on the periodical signalserving as the reference and the number of circulations acquired by saidacquisition unit.
 5. The apparatus according to claim 1, wherein saidinput/output module packetizes data and sends the packet to the ringbus, and receives the data that has undergone the predeterminedprocessing by said plurality of data process modules.
 6. The apparatusaccording to claim 1, wherein said acquisition unit calculates thenumber of circulations from a use order and an arrangement order of saidplurality of data process modules.
 7. The apparatus according to claim1, wherein said acquisition unit counts the number of circulations ofthe input data through the ring bus.
 8. The apparatus according to claim1, wherein said change unit shortens a period by setting the frequencythat decides the period to a frequency multiplied by the number ofcirculations.
 9. A data processing apparatus which circulates a packeton a ring bus by connecting a plurality of communication modules to thering bus and causing each communication module to send the packet to anadjacent communication module in synchronism with a predeterminedperiodical signal, comprising: a plurality of data process modules eachconnected to a corresponding one of the plurality of communicationmodules to process data held in the packet; an input/output moduleconnected to at least one of the plurality of communication modules toreceive/output data from/to the communication module; a measuring unitconfigured to measure an amount of data flowing through the ring bus;and a change unit configured to change a frequency of the periodicalsignal based on the data amount measured by said measuring unit.
 10. Amethod of controlling a data processing apparatus which circulates apacket on a ring bus by connecting a plurality of communication modulesto the ring bus and causing each communication module to send the packetto an adjacent communication module in synchronism with a predeterminedperiodical signal, comprising: a plurality of data processing steps ofcausing data process modules each connected to a corresponding one ofthe plurality of communication modules to process data held in thepacket; an input/output step of receiving/outputting data from/to atleast one of the plurality of communication modules; an acquisition stepof acquiring the number of circulations of data input in theinput/output step through the ring bus until the data completespredetermined processing and is output; and a change step of changing afrequency of the periodical signal in accordance with the number ofcirculations.